Reference Design
Introduction
The reference design consists of the modules DisplayPort TX (DPTX), DisplayPort RX (DPRX), Video Toolbox (VTB), PHY and application. The block diagram is shown below.
The VTB is a collection of video helper modules. It has a timing generator, colorbar generator, FIFO and video clock recovery.
The reference design has two operation modes; colorbar and pass-through. In colorbar mode the test pattern, generated by the VTB, is transmitted by the DPTX to the DisplayPort sink device. When the pass-through mode is selected, the video coming from the DisplayPort source is captured by the DPRX. Then the video is forwarded to the DPTX through the VTB.
The application has a RISC-V processor, memory (rom and ram) and a set of peripherals. The RISC-V processor runs the application code and DisplayPort IP-core host driver. The I2C peripheral is used to configure the external reference clock synthesizers (PHY and video clocks). The PHY registers are accessed through the DRP / LMMI / RCFG peripheral.
Running
This paragraph describes how to run the reference design on the board.
The reference design uses the Tentiva board
Tentiva is a video FMC board with DisplayPort sink and source connectors.
Mount the Tentiva board on the FMC HPC connector located on the FPGA development board. Use the plastic screws to secure the Tentiva board.
The reference design is available for the following platforms;
- AMD Zynq UltraScale+ ZCU102 evalution kit
- Inrevium ACDC A7 200T Evaluation Kit
- Intel Cyclone 10 GX FPGA development kit
- Intel Arria 10 GX FPGA development kit
- Lattice CertusPro-NX evaluation board
FMC voltage
At power-up the ZCU102 system controller reads the FMC EEPROM and sets the FMC voltage (VADJ). The EEPROM on the Tentiva FMC baseboard has a different layout and as a result the ZCU102 system controller doens’t power the FMC voltage. For correct operation the FMC VADJ has to be set to 1.8V manually. Use the ZCU102 system controller GUI to set the FMC VADJ voltage. Click here for more information on the ZCU102 system controller GUI. The FMC voltage can also be set through the UART. Click here for more information.
Transceiver
The reference design uses the GTH transceiver. The CPLL is used for the TX and the QPLL
The jumpers JP1 (TXD_UART) and JP2 (RXD_UART) must be installed.
Connect the external DisplayPort sink (eg. monitor) to the DPTX connector. This connector is labelled DPTX in the board picture. The DisplayPort source device (eg PC) is connected to the DPRX connector. This connector is labelled DPRX.
Connect the host PC to the FPGA boards USB interface. Open a serial terminal and set the baudrate to 115200. In the terminal application a CR must be added to the incoming LF for the RX data.
Download the FPGA bitstream into the FPGA using the FPGA vendor programming tool. After the FPGA was succesfully configured, you should see the welcome message on the terminal.
The application shows the target FPGA board. Also it shows the Tentiva base- and mezzanine boards information.
The application configures the DPTX and DPRX IP-cores. It pings the DPTX IP-core to verify the DPTX IP-core is up and running. Same is done for the DPRX IP-core. Additionally for the DPRX the edid is written and the hot plug detect (HPD) is asserted.
Colorbar
After the menu options, you should see that the DPTX detected the hot plug (HPD) and it succesfully trained the link. Press z for the colorbar mode. Then select one of the video resolutions. After selecting the video resolution the DPTX you should see the colorbar pattern on the DisplayPort sink device.
Pass-through
When the DisplayPort source video is enabled, you should see that the DPRX has succesfully trained and the link is up. Also it shows the detected incoming video parameters (in this example 1080p). Press x to enable the pass-through mode. You should see the video from the DisplayPort source device displayed on the DisplayPort sink device.
