PHY
The PHY module incorporates the high-speed transceivers (SerDes), which are external to the DP IP-cores. This module is generated by the transceiver wizard within the FPGA tool. The DisplayPort reference design comes with a PHY driver. The driver is responsible to configure the SerDes. Below is an overview of the driver configuration for each FPGA architecture. This configuration is easily modifiable to meet specific design requirements. The reference clocks are generated by the Tentiva GT clock generator.
AMD UltraScale(+)
Serdes: GTH
Transmitter PLL: CPLL
Receiver PLL: QPLL0
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 270 | 270 |
| HBR (2.7) | 270 | 270 |
| HBR2 (5.4) | 270 | 270 |
| HBR3 (8.1) | 270 | 270 |
AMD Artix-7
Serdes: GTP
Transmitter PLL: PLL0
Receiver PLL: PLL1
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 135 | 135 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
Intel Cyclone 10 GX
Transmitter PLL: ATX PLL
Receiver PLL: Channel PLL
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 135 | 135 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
Intel Arria 10 GX
Transmitter PLL: ATX PLL
Receiver PLL: Channel PLL
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 135 | 135 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
| HBR3 (8.1) | 135 | 135 |
Lattice CertusPro-NX
Transmitter PLL: Tx PLL
Receiver PLL: CDR PLL
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 81 | 81 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |