DP21RX mezzanine pins
| Name | FMC Pin | Decription |
|---|---|---|
| HPD | H25 | Hot Plug Detect |
| AUX_TX | G25 | AUX communication transmit |
| AUX_OE | G24 | AUX communication output enable |
| AUX_RX | G22 | AUX communication receive |
| CABDET# | H26 | Cable detect |
| I2C_SEL | G21 | I2C interface select 0 - I2C MZ / 1 - I2C FMC |
| I2C_SCL_MZ | H14 | I2C clock Mezzanine |
| I2C_SDA_MZ | H13 | I2C data Mezzanine |
| I2C_SCL_FMC | H14 | I2C clock FMC |
| I2C_SDA_FMC | H13 | I2C data FMC |
| ML_0_P | C6 | DP Lane 0 positive |
| ML_0_N | C7 | DP Lane 0 negative |
| ML_1_P | A2 | DP Lane 1 positive |
| ML_1_N | A3 | DP Lane 1 negative |
| ML_2_P | A6 | DP Lane 2 positive |
| ML_2_N | A7 | DP Lane 2 negative |
| ML_3_P | A10 | DP Lane 3 positive |
| ML_3_N | A11 | DP Lane 3 negative |
DP21TX mezzanine pins
| Name | FMC Pin | Decription |
|---|---|---|
| HPD# | G37 | Hot Plug Detect |
| AUX_TX | G30 | AUX communication transmit |
| AUX_OE | H28 | AUX communication output enable |
| AUX_RX | H29 | AUX communication receive |
| I2C_SEL | G31 | I2C interface select 0 - I2C MZ / 1 - I2C FMC |
| I2C_SCL_MZ | H32 | I2C clock Mezzanine |
| I2C_SDA_MZ | H31 | I2C data Mezzanine |
| I2C_SCL_FMC | C30 | I2C clock FMC |
| I2C_SDA_FMC | C31 | I2C data FMC |
| ML_0_P | C2 | DP Lane 0 positive |
| ML_0_N | C3 | DP Lane 0 negative |
| ML_1_P | A22 | DP Lane 1 positive |
| ML_1_N | A23 | DP Lane 1 negative |
| ML_2_P | A26 | DP Lane 2 positive |
| ML_2_N | A27 | DP Lane 2 negative |
| ML_3_P | A30 | DP Lane 3 positive |
| ML_3_N | A31 | DP Lane 3 negative |
Reference clock
At startup, the onboard PHY clock generator is pre-configured to synthesize the following frequencies;
| Clock | Frequency |
|---|---|
| GBTCLK0 | 135 MHz |
| GBTCLK1 | 150 MHz |
I2C devices
The Tentiva board includes several I2C devices connected via the FMC I2C interface. The table below lists the I2C addresses for these devices.
| Device | 12C Address |
|---|---|
| System controller | 0x4D |
| Baseboard EEPROM | 0x50 |
| DP21RX - EEPROM | 0x53 |
| DP21RX - PS8384 | 0x10 |
| DP21TX - EEPROM | 0x57 |
| DP21TX - TDP2004 | 0x18 |
System Controller
The Tentiva board features a system controller that allows the user to configure the PHY and VID clock synthesizers. This system controller is accessible via the I2C interface
Registers
| Offset | Description | RW |
|---|---|---|
| 0x00 | Version | RO |
| 0x01 | Control | RW |
| 0x02 | Status | RO |
| 0x03 | PHY clock | WO |
| 0x04 | VID clock | WO |
Version Register
| Bit | Name | Description |
|---|---|---|
| 3:0 | MINOR_VER | Minor version |
| 7:4 | MAJOR_VER | Major version |
Control Register
| Bit | Name | Description |
|---|---|---|
| 0 | CB1_SEL | CB1 select (U3) 0 - Select reference clock from MZ0; 1 - Select clock from MZ1 |
| 1 | CB2_SEL | CB2 select (U5) 0 - Route clock from PLL (U4) to FMC; 1 - Route clock from CB1 (U3) to FMC |
| 7:2 | RSVD | Reserved |
Status Register
| Bit | Description |
|---|---|
| 0 | PHY clock lock |
| 1 | VID clock lock |
| 7:2 | Reserved |
PHY clock Register
When this register is written, the PHY clock synthesizer is updated with the new frequency.
The frequency format is in kHz.
Eg. Write value 270000 into this register to generate a 270 MHz clock on PHY clock output.
| Bit | Description |
|---|---|
| 7:0 | Frequency Byte (low) |
| 15:8 | Frequency Byte (mid1) |
| 23:16 | Frequency Byte (mid2) |
| 31:24 | Frequency Byte (high) |
VID clock Register
When this register is written, the VID clock synthesizer is updated with the new frequency.
The frequency format is in kHz.
| Bit | Description |
|---|---|
| 7:0 | Frequency Byte (low) |
| 15:8 | Frequency Byte (mid1) |
| 23:16 | Frequency Byte (mid2) |
| 31:24 | Frequency Byte (high) |