Receiver

The HDMI receiver (HDMIRX) receives video from a HDMI source device. The core consists of two main layers; the system controller (SC) and link layer (LNK). The system controller is responsible for communication with the upstream HDMI source device and bring up the link. The link layer handles the (video) data transport.

The HDMIRX parameters are shown in the table below:

Name	Type	Description	Values
P_VENDOR	String	Vendor	LSC
P_BEAT	Integer	Beat value	50
P_SPL	Integer	Symbols per lane	2, 4
P_PPC	Integer	Pixels per clock	2, 4
P_BPC	Integer	Bits per component	8

The HDMIRX signals are shown in the table below:

Name	Clock	Description	Width
SYS_RST_IN	SYS_CLK	System reset	1
SYS_CLK_IN	SYS_CLK	System clock (50 MHz)	1
HOST_IF	SYS_CLK	Host interface	APB
HOST_IRQ_OUT	SYS_CLK	Host interrupt	1
CB_IN	SYS_CLK	Cable Detect	1
HPD_OUT	SYS_CLK	Hot Plug Detect	1
HB_OUT	SYS_CLK	Heartbeat	1
DDC_SCL_INOUT	SYS_CLK	Display Data Communication Clock	1
DDC_SDA_INOUT	SYS_CLK	Display Data Communication Data	1
TMDS_CLK_IN	-	TMDS clock input	1
LNK_CLK_IN	LNK_CLK	Link clock	1
LNK_DAT_IN	LNK_CLK	Link data	3 * P_SPL * 10
VID_VS_OUT	LNK_CLK	Video vertical sync	P_PPC
VID_HS_OUT	LNK_CLK	Video horizontal sync	P_PPC
VID_R_OUT	LNK_CLK	Video red	P_PPC * P_BPC
VID_G_OUT	LNK_CLK	Video green	P_PPC * P_BPC
VID_B_OUT	LNK_CLK	Video blue	P_PPC * P_BPC
VID_DE_OUT	LNK_CLK	Video data enable	P_PPC

Link Interface (LNK)

The link interface connects the HDMIRX with the FPGA serdes. The link interface signals have the prefix LNK_. The link clock (LNK_CLK_IN) is generated by the FPGA serdes. The link clock frequency depends on the actual video resolution. The link data (LNK_DAT_IN) is directly coming from the FPGA serdes.

Video Interface (VID)

The HDMIRX has an native video interface. The interface can support 2 or 4 pixels per clock. The video interface signals listed in the signal table have the prefix VID_. The diagrams below show the waveform and pixel mappings of the various configurations.

Figure 2: Video timing - 2 pixels per clock (click on the image to enlarge it)

Figure 3: Video timing - 4 pixels per clock (click on the image to enlarge it)