Transmitter
The HDMI transmitter (HDMITX) consists of two main layers: the system controller (SC) and link layer (LNK).
The system controller is responsible for communication with the downstream HDMI sink device and bring up the link.
| Name | Type | Description | Values |
|---|---|---|---|
| P_VENDOR | String | Vendor | LSC |
| P_BEAT | Integer | Beat value | 50 |
| P_SPL | Integer | Symbols per lane | 2, 4 |
| P_PPC | Integer | Pixels per clock | 2, 4 |
| P_BPC | Integer | Bits per component | 8 |
| Name | Clock | Description | Width |
|---|---|---|---|
| SYS_RST_IN | SYS_CLK | System reset | 1 |
| SYS_CLK_IN | SYS_CLK | System clock (50 MHz) | 1 |
| HOST_IF | SYS_CLK | Host interface | APB |
| HOST_IRQ_OUT | SYS_CLK | Host interrupt | 1 |
| HPD_IN | SYS_CLK | Hot Plug Detect | 1 |
| HB_OUT | SYS_CLK | Heartbeat | 1 |
| DDC_SCL_INOUT | SYS_CLK | Display Data Communication Clock | 1 |
| DDC_SDA_INOUT | SYS_CLK | Display Data Communication Data | 1 |
| VID_VS_IN | LNK_CLK | Video vertical sync | P_PPC |
| VID_HS_IN | LNK_CLK | Video horizontal sync | P_PPC |
| VID_R_IN | LNK_CLK | Video red | P_PPC * P_BPC |
| VID_G_IN | LNK_CLK | Video green | P_PPC * P_BPC |
| VID_B_IN | LNK_CLK | Video blue | P_PPC * P_BPC |
| VID_DE_IN | LNK_CLK | Video data enable | P_PPC |
| LNK_CLK_IN | LNK_CLK | Link clock | 1 |
| LNK_DAT_OUT | LNK_CLK | Link data | 4 * P_SPL * 10 |
Video Interface
The HDMITX has a native video interface and supports 2 or 4 pixels per clock. All video signals (prefixed with VID_) The HDMITX has a native video interface. The interface can support 2 or 4 pixels per clock. The video interface signals listed in the signal table have the prefix VID_ All video signals are high active. The video clock (VID_CLK_IN) runs at the pixel clock divided by the pixels per clock (2 or 4). For example with video resolution 1080p60 the pixel clock is 148.5 MHz. In 2 pixels per clock configuration the video clock runs at 74.25 MHz. It has a frequency of 37.125 MHz in 4 pixels per clock. The video clock must be stable and is generated by a PLL. The DPTX can support any video timing as long as the horizontal video timing is dividable by the number of pixels per clock (2 or 4). The figures below shows the video timing and pixel mapping.
Figure 2: Video timing - 2 pixels per clock (click on the image to enlarge it)
Figure 3: Video timing - 4 pixels per clock (click on the image to enlarge it)
Link Interface
The link interface connects DPTX to the FPGA serdes. Signals are prefixed with LNK_. The link interface connects the DPTX with the FPGA serdes. The link interface signals have the prefix LNK_ The link clock (LNK_CLK_IN) is generated by the FPGA serdes. The link clock frequency depends on the actual link rate. The link data (LNK_DAT_OUT) is directly routed to the FPGA serdes. See the DP reference design for the mapping.