System Controller
The Tentiva board features a system controller that allows the user to configure the PHY and VID clock synthesizers. This system controller is accessible via the I2C interface.
Registers
| Offset | Description | RW |
|---|---|---|
| 0x00 | Version | RO |
| 0x01 | Control | RW |
| 0x02 | Status | RO |
| 0x03 | PHY clock | WO |
| 0x04 | VID clock | WO |
Version Register
| Bit | Name | Description |
|---|---|---|
| 3:0 | MINOR_VER | Minor version |
| 7:4 | MAJOR_VER | Major version |
Control Register
| Bit | Name | Description |
|---|---|---|
| 0 | MZ_CLK_SEL | Mezzanine Clock Select 0 - Select reference clock from MZ0; 1 - Select clock from MZ1 |
| 1 | GT_REF_CLK_SEL | GT Reference Clock Select 0 - GT reference clock from PLL; 1 - GT reference clock from mezzanine clock |
| 7:2 | RSVD | Reserved |
Status Register
| Bit | Description |
|---|---|
| 0 | PHY clock lock |
| 1 | VID clock lock |
| 7:2 | Reserved |
PHY clock Register
When this register is written, the PHY clock synthesizer is updated with the new frequency. The frequency format is in kHz. Eg. Write value 270000 into this register to generate a 270 MHz clock on PHY clock output.
| Bit | Description |
|---|---|
| 7:0 | Frequency Byte (low) |
| 15:8 | Frequency Byte (mid1) |
| 23:16 | Frequency Byte (mid2) |
| 31:24 | Frequency Byte (high) |
VID clock Register
When this register is written, the VID clock synthesizer is updated with the new frequency. The frequency format is in kHz.
| Bit | Description |
|---|---|
| 7:0 | Frequency Byte (low) |
| 15:8 | Frequency Byte (mid1) |
| 23:16 | Frequency Byte (mid2) |
| 31:24 | Frequency Byte (high) |