Repository

The DP IP-cores and reference designs can be downloaded from the Github repository

The repository file structure is listed below:

                    ├─ gateware                          - Gateware folder
                    │  └─ src                            - IP-core sources
                    │     ├─ lib                         - Library
                    │     ├─ misc                        - Miscellaneous (PHY controllers, I2C, APB bridge)
                    │     ├─ pm                          - Policy maker
                    │     ├─ rx                          - DP RX
                    │     ├─ tx                          - DP TX
                    │     └─ vtb                         - Video toolbox
                    ├─ software                          - Software folder
                    │  ├─ pm                             - Policy maker images (ROM and RAM)
                    │  └─ src                            - Source folder
                    │     ├─ app                         - Host driver
                    │     ├─ shared                      - Tokens shared with the policy maker
                    │     ├─ tentiva                     - Tentiva drivers
                    │     └─ vtb                         - Video toolbox driver
                    └─ reference                         - Reference designs
                       ├─ amd                            - AMD Zynq UltraScale+
                       │  ├─ gateware/ref                - zu9eg_zcu102 (ZCU102), zu4cg_xu6_st1 (Mercury+ XU6)
                       │  └─ software                    - Application (src) and its build (build/dp_app)
                       ├─ altera                         - Altera Agilex 5
                       │  ├─ gateware/ref                - ag5e_065a_mdk (modular development kit)
                       │  └─ software                    - Application (src) and its build (build/dp_app)
                       └─ lsc                            - Lattice
                          ├─ gateware/propel             - Propel SoC scripts
                          ├─ gateware/ref                - lav_g70_versa_evn (Avant), lfcpnx_evn (CertusPro-NX)
                          └─ software                    - Application (src) and the Propel SDK workspace
            

The policy maker firmware is delivered as pre-compiled images in software/pm. The application loads them into the policy makers of the DPTX and DPRX at start-up (see Driver). The AMD projects use the memory files (.mem) of the same images as the initial memory contents.

Single-file IP-cores

Every release on GitHub also contains the IP-cores as single files (transmitter, receiver, policy maker and video toolbox), together with the libraries they need. This is the easiest way to add the DP IP-core to an FPGA project.

Reference design

Every vendor folder in reference has a README with the requirements and the build steps. The gateware is built with a project script in the synthesis folder of the board; the script creates the project, the vendor IP and the processor system, and runs the implementation. The output of the vendor tools is not in the repository. See Reference Design for the setup, the programming and the console.

AMD Zynq UltraScale+

Vivado 2025.1. The application is built with the Arm GNU toolchain 13.2 (aarch64-none-elf), cmake and ninja; the build script downloads the toolchain when it is not installed. <board> is zu9eg_zcu102 or zu4cg_xu6_st1.

1. Create the folder reference/amd/gateware/syn/<board> and change to it
2. Run the project script: vivado -mode batch -source ../../ref/<board>/build_proj.tcl
3. Build the application: reference/amd/software/build/dp_app/build.sh <board>

Altera Agilex 5

Quartus Prime Pro 26.1.1. The application is built with the Arm GNU toolchain 13.2 (aarch64-none-elf), cmake and ninja.

1. Create the folder reference/altera/gateware/syn/ag5e_065a_mdk and change to it
2. Run the project script: quartus_sh -t ../../ref/ag5e_065a_mdk/build_proj.tcl
3. Build the application and add it to the bitstream: reference/altera/software/build/dp_app/build.sh

Lattice Avant and CertusPro-NX

Radiant 2026.1 and Propel 2026.1. The steps are for the Avant, with the CertusPro-NX names in brackets.

1. In reference/lsc/gateware/propel create the Propel SoC: propelbldc < create_dp_soc_lav.tcl (create_dp_soc_lfcpnx.tcl)
2. Open the workspace reference/lsc/software/workspace in Propel SDK, import the project dp_app_lav (dp_app_lfcpnx), generate its BSP from the SoC and build it
3. Create the folder reference/lsc/gateware/syn/lav_g70_versa_evn (lfcpnx_evn) and change to it
4. Run the project script: radiantc ../../ref/lav_g70_versa_evn/build_proj.tcl