Transmitter
The HDMI transmitter (HDMITX) consists of two main layers: the system controller (SC) and the link layer (LNK). The system controller is responsible for communication with the downstream HDMI sink device and bringing up the link. The link layer handles the (video) data transport.
| Name | Type | Description | Values |
|---|---|---|---|
| P_VENDOR | String | Vendor | LSC |
| P_BEAT | Integer | Beat value | 50 |
| P_SPL | Integer | Symbols per lane | 2, 4 |
| P_PPC | Integer | Pixels per clock | 2, 4 |
| P_BPC | Integer | Bits per component | 8 |
| Name | Clock | Description | Width |
|---|---|---|---|
| SYS_RST_IN | SYS_CLK | System reset | 1 |
| SYS_CLK_IN | SYS_CLK | System clock (50 MHz) | 1 |
| HOST_IF | SYS_CLK | Host interface | APB |
| HOST_IRQ_OUT | SYS_CLK | Host interrupt | 1 |
| HPD_IN | SYS_CLK | Hot Plug Detect | 1 |
| HB_OUT | SYS_CLK | Heartbeat | 1 |
| DDC_SCL_INOUT | SYS_CLK | Display Data Communication Clock | 1 |
| DDC_SDA_INOUT | SYS_CLK | Display Data Communication Data | 1 |
| VID_VS_IN | LNK_CLK | Video vertical sync | P_PPC |
| VID_HS_IN | LNK_CLK | Video horizontal sync | P_PPC |
| VID_DAT_IN | LNK_CLK | Video data | 3 * P_PPC * P_BPC |
| VID_DE_IN | LNK_CLK | Video data enable | P_PPC |
| LNK_CLK_IN | LNK_CLK | Link clock | 1 |
| LNK_DAT_OUT | LNK_CLK | Link data | 4 * P_SPL * 10 |
Clocking
The core uses two clock domains. The system clock (SYS_CLK, 50 MHz) drives the system controller and the host interface (APB). The link clock (LNK_CLK) drives the video and link interfaces and is derived from the pixel clock divided by the number of pixels per clock. The video interface therefore runs synchronously with the link layer.
Video Interface
The HDMITX has a native video interface and supports 2 or 4 pixels per clock. The video interface signals listed in the signal table have the prefix VID_ and are high active. The video clock (VID_CLK_IN) runs at the pixel clock divided by the pixels per clock (2 or 4). For example with video resolution 1080p60 the pixel clock is 148.5 MHz. In 2 pixels per clock configuration the video clock runs at 74.25 MHz. It has a frequency of 37.125 MHz in 4 pixels per clock. The video clock must be stable and is generated by a PLL. The HDMITX can support any video timing as long as the horizontal video timing is dividable by the number of pixels per clock (2 or 4). The pixel mapping of the video interface for each supported color space (RGB 4:4:4, YCbCr 4:4:4 and YCbCr 4:2:2) is described in the HDMI Mapping section.
Link Interface
The link interface connects the HDMITX to the FPGA serdes. The link interface signals are prefixed with LNK_. The link clock (LNK_CLK_IN) is generated by the FPGA serdes and its frequency depends on the actual link rate. The link data (LNK_DAT_OUT) is directly routed to the FPGA serdes. See the HDMI reference design for the mapping.