PHY
The PHY module incorporates the high-speed transceivers (SerDes), which are external to the DP IP-cores. This module is generated by the transceiver wizard within the FPGA tool. The DP IP-cores connect to the PHY through the link interface: the DPTX delivers the link symbols to the transmitters and the DPRX takes the link symbols from the receivers, with 2 or 4 symbols per lane per link clock (P_SPL). The link clocks are the word clocks of the transceivers, so their frequency follows the line rate.
The DisplayPort reference design comes with a PHY driver for every FPGA architecture. The driver is responsible to configure the SerDes and is called by the application from the DP callbacks:
- Line rate - during link training the transmitter and the receiver change the line rate (RBR, HBR, HBR2 and HBR3). The transmitter and the receiver are programmed independently, so the DPTX and the DPRX can run at different line rates.
- Reset - the receiver is reset and recalibrated after a line rate change, so that the clock data recovery locks to the incoming link.
- Voltage swing and pre-emphasis - the transmitter applies the voltage swing and pre-emphasis levels that the sink requests during link training.
Below is an overview of the PHY configuration for each FPGA architecture. This configuration is easily modifiable to meet specific design requirements. Unless noted otherwise, the reference clocks are generated by the Tentiva GT clock generator.
AMD Zynq UltraScale+
Serdes: GTHE4, transceiver wizard with the 8b/10b encoder and decoder
Transmitter PLL: QPLL1
Receiver PLL: CPLL
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 270 | 270 |
| HBR (2.7) | 270 | 270 |
| HBR2 (5.4) | 270 | 270 |
| HBR3 (8.1) | 270 | 270 |
The PLLs are used as in the AMD Video PHY Controller for DisplayPort, so that the transmitter and the receiver change their line rate independently. The QPLL1 VCO runs between 8.1 and 12.96 GHz, the CPLL VCO between 2.7 and 4.05 GHz.
The line rate changes through the DRP. For every line rate the attribute values of the transceiver IP are written, for the transmitter and the receiver apart. These DRP tables are generated from the transceiver IP at every line rate (amd/scripts/gen_phy_gth_dr.py). The DRP and free running clock is 40 MHz; the receiver CPLL runs the CPLL calibration of the transceiver wizard.
The reference clock comes from the Tentiva FMC. The receive user clock comes from the RX master channel, which must be the channel of DP lane 0. With one or two lanes the CDR of an unused channel runs free.
HBR3 is tested on the ZCU102 (XCZU9EG, speed grade -2) and on the Enclustra Mercury+ XU6 (XCZU4CG, speed grade -1). The AMD Video PHY Controller supports HBR3 for DisplayPort only from speed grade -2.
AMD Artix-7
Serdes: GTP
Transmitter PLL: PLL0
Receiver PLL: PLL1
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 135 | 135 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
Altera Agilex 5
Serdes: GTS, PMA Direct PHY in DisplayPort mode
Transmitter PLL: TX PLL, with spread spectrum support
Receiver PLL: CDR
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 150 | 150 |
| HBR (2.7) | 150 | 150 |
| HBR2 (5.4) | 150 | 150 |
| HBR3 (8.1) | 150 | 150 |
The reference clock comes from the Si549 oscillator on the Agilex 5 modular development kit. The line rate changes through the PCS rate register with the profiles that are generated in the IP.
Lattice CertusPro-NX
Transmitter PLL: Tx PLL
Receiver PLL: CDR PLL
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 81 | 81 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
Lattice Avant
Serdes: MPPHY
Transmitter PLL: MPLL
Receiver PLL: CDR
| LineRate (Gbps) | TX Reference Clock (MHz) | RX Reference Clock (MHz) |
|---|---|---|
| RBR (1.6) | 135 | 135 |
| HBR (2.7) | 135 | 135 |
| HBR2 (5.4) | 135 | 135 |
| HBR3 (8.1) | 135 | 135 |
The line rate registers come from a table that is generated out of the PHY profiles. The transmitter and the receiver each set their own line rate.
The voltage swing and pre-emphasis are set with the main and post cursor of the transmitter. The peak amplitude is main + post cursor (24 is the full swing), the de-emphasised level main - post cursor, so the DP levels are exact ratios.