Overview
Introduction
The HDMI IP-core implements the HDMI 2.0 interface for FPGA devices and supports both transmit (TX) and receive (RX) operation. Video is carried over the three TMDS data lanes; the core supports resolutions up to 4K at 60 Hz in 8-bit color.
Internally the design is organised in two layers. The system controller (SC) is a small embedded processor that runs firmware to bring up and manage the link — including hot-plug detection and EDID/DDC exchange with the connected device. The link layer (LNK) handles the video datapath: TMDS encoding on the transmit side and TMDS decoding and alignment on the receive side. The core is written in SystemVerilog, is parameterisable for pixels-per-clock and vendor target, and ships with a software driver to control it from the host system.
Features
- HDMI 2.0
- Native video
- Dual and quad pixels per clock (PPC)
- Color depth: 8 (BPC)
- Color space: RGB 4:4:4, YCbCr 4:4:4 & YCbCr 4:2:2
Resources
The following FPGA vendors are supported:
- Lattice Semiconductor
The tables below show the device utilization for the various FPGA devices.
| Module | LUT | FF | EBR | DSP |
|---|---|---|---|---|
| HDMI TX (HDMITX) | 8945 | 4545 | 10 | 0 |
| HDMI RX (HDMIRX) | 11078 | 5064 | 10 | 0 |
- Device LFCPNX-100-9LFG672C
- Radiant software 2026.1.0.37.0 (Synplify Pro)
- SPL - 4 / PPC - 4 / BPC - 8
- Date: July 9th, 2026
| Module | LUT | FF | EBR | DSP |
|---|---|---|---|---|
| HDMI TX (HDMITX) | 6335 | 3454 | 5 | 0 |
| HDMI RX (HDMIRX) | 8024 | 4092 | 5 | 0 |
- Device LAV-AT-X70-1LFG1156C
- Radiant software 2026.1.0.37.0 (Synplify Pro)
- SPL - 2 / PPC - 2 / BPC - 8
- Date: July 9th, 2026
Known Limitations
HDMITX / HDMIRX
- Any video resolution is supported, however only video resolutions tested are 720p50/60, 1080p50/60, 1440p50/60 and 4kp50/60
- Video 8-bit only is supported.
- Audio and meta packets are not supported.