Overview
Introduction
The HDMI IP-core implements the HDMI 2.0 interface for FPGA devices. It supports both transmit (TX) and receive (RX) operation and can be configured for different video formats and pixel rates. The design is written in SystemVerilog and organised in separate functional blocks for the video path, link layer, and control interface. A software driver is provided to control and configure the HDMI IP-core from the host system.
Features
- HDMI 2.0
- Native video
- Dual and quad pixels per clock (PPC)
- Color depth: 8 (BPC)
- Color space: RGB 4:4:4 & YUV 4:4:4
Resources
The following FPGA vendors are supported:
- Lattice Semiconductor
The tables below show the device utilization for the various FPGA devices.
Lattice CertusPro-NX
| Module | LUT | FF | EBR | DSP |
|---|---|---|---|---|
| HDMI TX (HDMITX) | 7281 | 3263 | 10 | 0 |
| HDMI RX (HDMIRX) | 9859 | 4422 | 10 | 0 |
- Device LFCPNX-100-9LFG672C
- Radiant software 2025.2.0.48.0 (Synplify Pro)
- SPL - 4 / PPC - 4 / BPC - 8
- Date: February 21, 2026
Lattice Avant
| Module | LUT | FF | EBR | DSP |
|---|---|---|---|---|
| HDMI TX (HDMITX) | 5738 | 2389 | 5 | 0 |
| HDMI RX (HDMIRX) | 7415 | 3405 | 5 | 0 |
- Device LAV-AT-X70-1LFG1156C
- Radiant software 2025.2.0.48.0 (Synplify Pro)
- SPL - 2 / PPC - 2 / BPC - 8
- Date: February 21, 2026
Known Limitations
HDMITX / HDMIRX
- Any video resolution is supported, however only video resolutions tested are 720p50/60, 1080p50/60, 1440p50/60 and 4kp50/60
- Video 8-bit only is supported.
- Audio and meta packets are not supported.