Introduction

The DisplayPort IP-core is a complete DisplayPort 1.4a link for FPGA implementation, in both directions: a transmitter that drives a sink, and a receiver that takes video from a source.

Each core is organised in two layers. The policy maker (PM) is a small RISC-V processor running firmware that owns the protocol: the AUX channel, hot plug detect, capability exchange and link training. The link layer (LNK) carries the data: mapping video onto the lanes, inserting the main stream attributes and secondary data packets, scrambling, and lane skew on the transmit side, with the mirror image on the receive side.

That split is what makes the core autonomous. Link training runs on the policy maker's own timers, so the application processor is free of it — it asks for a link at a given rate and hears back what came of it. The core is written in SystemVerilog with a resource optimized footprint, is parameterisable for lanes, pixels per clock and vendor target, and ships with a thin C driver.

Features

• DisplayPort 1.4a
• RBR, HBR, HBR2 and HBR3 line rates
• Support for 1, 2 and 4 DP lanes
• Native video and AXI stream interfaces
• Single Stream transport mode (SST)
• Multi Stream transport mode (MST)
• Dual and quad pixels per clock (PPC)
• Color depth: 8 & 10-bits (BPC)
• Color space: RGB 4:4:4, YUV 4:4:4, YUV 4:2:2 and YUV 4:2:0
• Secondary Packet interface for audio and meta data
• Policy maker with on-chip RISC-V processor and firmware

Resources

The following FPGA vendors are supported:

• AMD
• Altera
• Lattice Semiconductor

The tables below show the device utilization for the various FPGA devices.

Module	LUT	FF	BRAM	DSP
DisplayPort TX (DPTX)	5531	3680	5	0
DisplayPort RX (DPRX)	6205	4210	8.5	0
Video Toolbox (VTB)	2045	3274	4.5	3

• Device XCZU9EG-FFVB1156-2 (ZCU102)
• BRAM in 36 Kb blocks (a RAMB18 counts as 0.5)
• Vivado software v2025.1
• SPL - 2 / PPC - 4 / BPC - 10
• Date: October 15, 2026

Module	LUT	FF	BRAM	DSP
DisplayPort TX (DPTX)	6414	4294	5	0
DisplayPort RX (DPRX)	7270	4973	8.5	0
Video Toolbox (VTB)	2046	3274	4.5	3

• Device XCZU4CG-SFVC784-1 (Enclustra Mercury+ XU6)
• BRAM in 36 Kb blocks (a RAMB18 counts as 0.5)
• Vivado software v2025.1
• SPL - 4 / PPC - 4 / BPC - 10
• Date: October 15, 2026

Module	LUT	FF	BRAM	DSP
DisplayPort TX (DPTX)	6163	3933	5	0
DisplayPort RX (DPRX)	6619	4199	5	0
Video Toolbox (VTB)	1243	2340	3	2

• Device XC7A200TFFG1156-2
• Vivado software v2023.1
• Quad pixel datapath
• Date: January 14, 2024

Module	ALM	FF	M20K	DSP
DisplayPort TX (DPTX)	5227	6717	8	0
DisplayPort RX (DPRX)	6418	6592	14	0
Video Toolbox (VTB)	1724	3136	7	2

• Device A5ED065AB32AE1V
• Logic element: ALM, one adaptive lookup table
• ALM: ALMs needed. FF: dedicated logic registers, including the Hyper-Registers in the routing
• Quartus Prime Pro software 26.1.1
• SPL - 2 / PPC - 4 / BPC - 10
• Date: October 15, 2026

Module	LUT	FF	EBR	DSP
DisplayPort TX (DPTX)	16449	7833	10	0
DisplayPort RX (DPRX)	18467	6070	17	0
Video Toolbox (VTB)	2999	2787	9	4

• Device LFCPNX-100-9LFG672C
• LUT: LUT4. FF: PFU registers. DSP: MULT9, MULT18 and ACC54 blocks
• Radiant software 2026.1.0.37.0 (Synplify Pro)
• SPL - 4 / PPC - 4 / BPC - 10
• Date: October 15, 2026

Module	LUT	FF	EBR	DSP
DisplayPort TX (DPTX)	15762	8377	5	0
DisplayPort RX (DPRX)	16915	6515	9	0
Video Toolbox (VTB)	2827	2770	5	7

• Device LAV-AT-X70-1LFG1156C
• LUT: LUT4. FF: PFU registers. DSP: MULT9, MULT18 and ACC54 blocks
• Radiant software 2026.1.0.37.0 (Synplify Pro)
• SPL - 4 / PPC - 4 / BPC - 10
• Date: October 15, 2026

Known Limitations

DPTX / DPRX

• The horizontal video timing must be dividable by the number of pixels per clock (PPC).
• Any video resolution is supported, however only video resolutions tested are 720p50/60, 1080p50/60, 1440p50/60 and 4kp50/60

VTB

• At start of the video the screen might flicker while the clock recovery module is locking to the incoming video stream.