Introduction
The DisplayPort IP-core is a complete DisplayPort 1.4a link for FPGA implementation, in both
directions: a transmitter that drives a sink, and a receiver that takes video from a source.
Each core is organised in two layers. The policy maker (PM) is a small RISC-V processor
running firmware that owns the protocol: the AUX channel, hot plug detect, capability exchange and link
training. The link layer (LNK) carries the data: mapping video onto the lanes, inserting
the main stream attributes and secondary data packets, scrambling, and lane skew on the transmit side,
with the mirror image on the receive side.
That split is what makes the core autonomous. Link training runs on the policy maker's own timers, so the
application processor is free of it — it asks for a link at a given rate and hears back what came of
it. The core is written in SystemVerilog with a resource optimized footprint, is parameterisable for
lanes, pixels per clock and vendor target, and ships with a thin C driver.
Max line rate
HBR3
8.1 Gbps per lane
Pixels per clock
2 / 4 PPC
Color space
RGB & YUV
YUV 4:4:4 · 4:2:2 · 4:2:0
Features
- DisplayPort 1.4a
- RBR, HBR, HBR2 and HBR3 line rates
- Support for 1, 2 and 4 DP lanes
- Native video and AXI stream interfaces
- Single Stream transport mode (SST)
- Multi Stream transport mode (MST)
- Dual and quad pixels per clock (PPC)
- Color depth: 8 & 10-bits (BPC)
- Color space: RGB 4:4:4, YUV 4:4:4, YUV 4:2:2 and YUV 4:2:0
- Secondary Packet interface for audio and meta data
- Policy maker with on-chip RISC-V processor and firmware
Resources
The following FPGA vendors are supported:
- AMD
- Altera
- Lattice Semiconductor
The tables below show the device utilization for the various FPGA devices.
AMD Ultrascale+
| Module | LUT | FF | BRAM | DSP |
|---|
| DisplayPort TX (DPTX) | 6268 | 4734 | 5 | 0 |
| DisplayPort RX (DPRX) | 7880 | 5041 | 8.5 | 0 |
| Video Toolbox (VTB) | 1257 | 2369 | 3.5 | 2 |
- Device XCZU9EG
- Vivado software v2024.1
- SPL - 2 / PPC - 4 / BPC - 10
- Date: May 4, 2026
AMD Artix-7
| Module | LUT | FF | BRAM | DSP |
|---|
| DisplayPort TX (DPTX) | 6163 | 3933 | 5 | 0 |
| DisplayPort RX (DPRX) | 6619 | 4199 | 5 | 0 |
| Video Toolbox (VTB) | 1243 | 2340 | 3 | 2 |
- Device XC7A200TFFG1156-2
- Vivado software v2023.1
- Quad pixel datapath
- Date: January 14, 2024
Altera Cyclone 10GX
| Module | ALM | REG | M20K | DSP |
|---|
| DisplayPort TX (DPTX) | 5391.1 | 5298 | 8 | 0 |
| DisplayPort RX (DPRX) | 6783.9 | 5495 | 8 | 0 |
| Video Toolbox (VTB) | 881.9 | 2631 | 3 | 1 |
- Device 10CX220YF780E5G
- Quartus Prime Pro software 24.1.0
- Dual pixel datapath
- Date: June 4, 2025
Altera Arria 10GX
| Module | ALM | REG | M20K | DSP |
|---|
| DisplayPort TX (DPTX) | 3588.3 | 3470 | 8 | 0 |
| DisplayPort RX (DPRX) | 3958.4 | 3833 | 8 | 0 |
| Video Toolbox (VTB) | 881.0 | 2628 | 3 | 1 |
- Device 10AX115S2F45I1SG
- Quartus Prime Pro software 23.2.0
- Dual pixel datapath
- Date: January 14, 2024
Lattice CertusPro-NX
| Module | LUT | FF | EBR | DSP |
|---|
| DisplayPort TX (DPTX) | 11782 | 4193 | 10 | 0 |
| DisplayPort RX (DPRX) | 15090 | 5058 | 17 | 0 |
| Video Toolbox (VTB) | 1865 | 2508 | 7 | 7 |
- Device LFCPNX-100-9LFG672C
- Radiant software 2025.2.0.48.0 (Synplify Pro)
- SPL - 4 / PPC - 4 / BPC - 10
- Date: May 6, 2026
Lattice Avant
| Module | LUT | FF | EBR | DSP |
|---|
| DisplayPort TX (DPTX) | 8896 | 3627 | 5 | 0 |
| DisplayPort RX (DPRX) | 9621 | 3897 | 5 | 0 |
| Video Toolbox (VTB) | 1706 | 2512 | 3 | 6 |
- Device LAV-AT-X70-1LFG1156C
- Radiant software 2025.1.1.308.0 (Synplify Pro)
- SPL - 2 / PPC - 2 / BPC - 10
- Date: December 14, 2025
Known Limitations
DPTX / DPRX
- The horizontal video timing must be dividable by the number of pixels per clock (PPC).
- Any video resolution is supported, however only video resolutions tested are 720p50/60, 1080p50/60, 1440p50/60 and 4kp50/60
VTB
- At start of the video the screen might flicker while the clock recovery module is locking to the incoming video stream.
