Overview
Introduction
The DisplayPort IP-core is a DisplayPort solution for FPGA implementation. It has a resource optimized footprint and it is written in SystemVerilog. A thin host driver is provided with the IP-core. The application software controls the IP-core using this driver.
Features
- DisplayPort 1.4a
- RBR, HBR, HBR2 and HBR3 line rates
- Support for 1, 2 and 4 DP lanes
- Native video and AXI stream interfaces
- Single Stream transport mode (SST)
- Multi Stream transport mode (MST)
- Dual and quad pixels per clock (PPC)
- Color depth: 8 & 10-bits (BPC)
- Color space: RGB 4:4:4 & YUV 4:4:4
- Secondary Packet interface for audio and meta data
Resources
The following FPGA vendors are supported:
- AMD
- Altera
- Lattice Semiconductor
The tables below show the device utilization for the various FPGA devices.
AMD Ultrascale+
| Module | LUT | FF | BRAM | DSP |
|---|---|---|---|---|
| DisplayPort TX (DPTX) | 6045 | 4687 | 5 | 0 |
| DisplayPort RX (DPRX) | 7344 | 4857 | 5 | 0 |
| Video Toolbox (VTB) | 1257 | 2369 | 3.5 | 2 |
- Device XCZU9EG
- Vivado software v2024.1
- SPL - 2 / PPC - 4 / BPC - 10
- Date: June 4, 2025
AMD Artix-7
| Module | LUT | FF | BRAM | DSP |
|---|---|---|---|---|
| DisplayPort TX (DPTX) | 6163 | 3933 | 5 | 0 |
| DisplayPort RX (DPRX) | 6619 | 4199 | 5 | 0 |
| Video Toolbox (VTB) | 1243 | 2340 | 3 | 2 |
- Device XC7A200TFFG1156-2
- Vivado software v2023.1
- Quad pixel datapath
- Date: January 14, 2024
Altera Cyclone 10GX
| Module | ALM | REG | M20K | DSP |
|---|---|---|---|---|
| DisplayPort TX (DPTX) | 5391.1 | 5298 | 8 | 0 |
| DisplayPort RX (DPRX) | 6783.9 | 5495 | 8 | 0 |
| Video Toolbox (VTB) | 881.9 | 2631 | 3 | 1 |
- Device 10CX220YF780E5G
- Quartus Prime Pro software 24.1.0
- Dual pixel datapath
- Date: June 4, 2025
Altera Arria 10GX
| Module | ALM | REG | M20K | DSP |
|---|---|---|---|---|
| DisplayPort TX (DPTX) | 3588.3 | 3470 | 8 | 0 |
| DisplayPort RX (DPRX) | 3958.4 | 3833 | 8 | 0 |
| Video Toolbox (VTB) | 881.0 | 2628 | 3 | 1 |
- Device 10AX115S2F45I1SG
- Quartus Prime Pro software 23.2.0
- Dual pixel datapath
- Date: January 14, 2024
Lattice CertusPro-NX
| Module | LUT | FF | EBR | DSP |
|---|---|---|---|---|
| DisplayPort TX (DPTX) | 11997 | 4101 | 10 | 0 |
| DisplayPort RX (DPRX) | 14442 | 4834 | 10 | 0 |
| Video Toolbox (VTB) | 1865 | 2508 | 7 | 7 |
- Device LFCPNX-100
- Radiant software 2024.2.1.330.0 (Synplify Pro)
- SPL - 4 / PPC - 4 / BPC - 10
- Date: June 4, 2025
Known Limitations
DPTX / DPRX
- The horizontal video timing must be dividable by the number of pixels per clock (PPC).
- Any video resolution is supported, however only video resolutions tested are 720p50/60, 1080p50/60, 1440p50/60 and 4kp50/60
VTB
- At start of the video the screen might flicker while the clock recovery module is locking to the incoming video stream.