Encoder

The JPEG encoder converts uncompressed YCbCr video streams into fully compliant baseline JPEG images with deterministic latency. The architecture is optimized for real-time video with support up to 4Kp60.
The encoder implements:

The JPEG encoder parameters are shown in the table below:
Name Type Description Values
P_VENDOR String Vendor LSC
P_HWIDTH Integer Horizontal line width 3840
P_PPC Integer Pixels per clock 4
P_BPC Integer Bits per component 8
The JPEG encoder signals are shown in the table below:
Name Clock Description Width
SYS_RST_IN SYS_CLK System reset 1
SYS_CLK_IN SYS_CLK System clock 1
VID_CLK_IN VID_CLK Video clock 1
HOST_IF SYS_CLK Host interface APB
HOST_IRQ_OUT SYS_CLK Host interrupt 1
VID_SOF_IN VID_CLK Start of frame 1
VID_DAT_IN VID_CLK Data 64
VID_EOL_IN VID_CLK End of line 1
VID_VLD_IN VID_CLK Valid 1
CS_RDY_IN VID_CLK Ready 1
CS_SOI_OUT VID_CLK Start of image 1
CS_EOI_OUT VID_CLK End of image 1
CS_DAT_OUT VID_CLK Data 64
CS_VLD_OUT VID_CLK Valid 1

Video Interface (VID)

The JPEG Encoder IP-core provides a high-throughput parallel video input interface. The interface accepts unpacked YCbCr 4:2:2 pixel data and supports multi-pixel-per-clock operation for efficient processing of high-resolution video streams. The video interface signals listed in the signal table have the prefix VID_. The diagram below show the timing waveform and pixel mapping.

AXIS Video Interface

Figure 1: AXI-stream video interface (click on the image to enlarge it)

Codestream Interface (CS)

The codestream interface provides the compressed JPEG bitstream output via a standard AXI4-Stream interface. This allows seamless integration with DMA engines, memory controllers, PCIe blocks, NVIDIA Hololink pipeline, or other AXI-based FPGA infrastructure.
Output Characteristics:

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