Overview

Parretto Video IP Cubes

Introduction

The JPEG Encoder IP-core turns a live video stream into fully compliant baseline JPEG images, inside the FPGA, while the frame is still arriving.

There is no frame buffer and no external memory in the datapath. Pixels enter the core four at a time, are gathered into 8×8 blocks and travel through the transform, quantizer and Huffman encoder as one continuous pipeline. The first compressed bytes leave the core once the first block row of the image has been read in — eight video lines, not a whole frame. That is what makes the latency low and, more importantly, predictable: the same picture always takes the same number of clocks.

4Kp60 is the top end, not the only setting. The same core encodes a VGA sensor feed or a 720p stream without changes — the image size is a run time setting that the host writes into the JPEG header, and only the maximum line width is fixed at synthesis time. Smaller pictures simply take fewer clocks.

The core is written in SystemVerilog and is parameterisable for line width, pixels per clock and vendor target. A host processor sets it up over an APB interface, using the plain C driver that ships with the core, and the compressed codestream comes out over a 64-bit stream that plugs straight into a DMA engine, a PCIe block or an NVIDIA Holoscan sensor bridge.

Max resolution
4Kp60
Pixels per clock
4 PPC
Color space
4:2:2
Color depth
8 BPC
Encoding latency
8 lines

The pipeline

Every stage runs at the video rate, so the whole chain is a straight line from pixels to codestream with no place where a frame has to be parked.

Pixels4 per clock
→
Blocks8×8
→
DCT2D transform
→
Quantizerluma, chroma
→
Zig-zagreorder
→
Huffman8 lanes
→
Codestream64 bit out

The encoder page has the block diagram and the signal description.

Compliant output

Baseline JPEG to ISO/IEC 10918-1 (ITU-T T.81), with the standard markers in place. The output opens in any viewer, decoder or browser without a special profile.

Eight Huffman lanes

The entropy encoder runs eight Huffman encoders side by side and merges their variable length codes back into one bitstream, so entropy coding keeps up with the four pixel per clock front end.

Deterministic latency

No frame buffer, no rate control loop and no external memory. Latency is set by the pipeline itself and does not move with picture content.

Features

Applications

Machine vision
Frame grabbers
Medical imaging
Broadcast contribution
Remote inspection
NVIDIA Holoscan sensor bridges

Resources

The following FPGA devices are supported:

The tables below show the device utilization.

Lattice CertusPro-NX
ModuleResolutionLUTFFEBRDSP
JPEG_ENC38401610572859718
JPEG_ENC19201592971898118
Lattice Avant
ModuleResolutionLUTFFEBRDSP
JPEG_ENC38401833074746718
JPEG_ENC19201809573786718
AMD Artix UltraScale+
ModuleResolutionLUTFFBRAMDSP
JPEG_ENC3840947183314218
JPEG_ENC1920944782353418
Altera Agilex 3
ModuleResolutionALMFFM20KDSP
JPEG_ENC3840907710778849
JPEG_ENC1920893011200689
Altera Agilex 5
ModuleResolutionALMFFM20KDSP
JPEG_ENC3840911310525849
JPEG_ENC1920895210608689

Notes