Reference Design

Introduction

The reference design shows the DisplayPort TX (DPTX) and DisplayPort RX (DPRX) IP-cores in a complete system. It consists of the DPTX, the DPRX, the Video Toolbox (VTB), the PHY and the application. The VTB is a collection of video helper modules. It has a timing generator, colorbar generator, FIFO and video clock recovery.

The application runs on the processor of the FPGA vendor: the Arm Cortex-A53 of the processing system on the AMD Zynq UltraScale+, the Arm Cortex-A55 of the hard processor system (HPS) on the Altera Agilex 5 and the RISC-V MC soft processor of Lattice Propel on the Lattice FPGAs. The application processor runs the application code and the DisplayPort IP-core host driver (see Driver). It controls the IP-cores and the other peripherals through a memory mapped bus. The link training, AUX and hot plug handling are done by the policy maker inside the DPTX and DPRX IP-cores, so the application only handles the events of the IP-cores.

The reference design has two operation modes; colorbar and pass-through. In colorbar mode the test pattern, generated by the VTB, is transmitted by the DPTX to the DisplayPort sink device. When the pass-through mode is selected, the video coming from the DisplayPort source is captured by the DPRX. Then the video is forwarded to the DPTX through the VTB. The clock recovery of the VTB steers the video clock on the Tentiva, so the DPTX video runs at the frequency of the DisplayPort source.

The I2C peripheral configures the reference clock synthesizers on the Tentiva (PHY and video clocks), or on the Agilex 5 the DisplayPort redrivers of the board. The PHY controller accesses the transceiver registers (DRP on AMD, reconfiguration interface on Altera, LMMI on Lattice) and controls the transceiver resets and line rate.

The reference design is available for the following platforms;

• AMD Zynq UltraScale+ ZCU102 evaluation kit
• Enclustra Mercury+ XU6 SoC module (Zynq UltraScale+ ZU4CG) on the Mercury+ ST1 base board
• Altera Agilex 5 E-Series 065A modular development kit
• Lattice Avant Versa board (LAV-AT-X70)
• Lattice CertusPro-NX evaluation board

AMD ZCU102

The ZCU102 reference design runs on the Zynq UltraScale+ XCZU9EG-FFVB1156-2 with the Tentiva on FMC HPC0. The block diagram is shown below.

Processing system

The application runs bare metal on Cortex-A53 core 0 of the processing system (PS), from the on-chip memory (OCM, 256 KB). The DDR memory is not used. The console is PS UART0, which is routed through the EMIO to the UART of the Tentiva. The PS supplies the system clock (100 MHz) and the DRP clock of the transceivers (40 MHz) to the programmable logic (PL). The interrupts of the DPTX and DPRX go to the interrupt controller (GIC) of the PS.

Programmable logic

The low power domain master port (M_AXI_HPM0_LPD) of the PS connects through an AXI SmartConnect to an AXI GPIO and an AXI to APB bridge. The APB bridge has a port of 4 KB for every IP-core and peripheral. The address map is shown below.

Address	Peripheral	Description
0x8000_0000	PIO	AXI GPIO. Output: DPTX and DPRX reset. Input: pixels per clock and bits per component of the design
0x8000_1000	DPTX	DisplayPort transmitter
0x8000_2000	VTB	Video toolbox
0x8000_3000	PHY	PHY controller (DRP, resets, line rate, voltage swing and pre-emphasis)
0x8000_4000	DPRX	DisplayPort receiver
0x8000_5000	I2C	I2C controller. The Tentiva is on channel 0 of the I2C mux U135 of the ZCU102

The PHY is the GTH transceiver quad X1Y2 (bank 229) with the 270 MHz reference clock of the Tentiva, see the PHY page. The receivers use the channel PLL (CPLL), the transmitters the quad PLL (QPLL1). The DPTX and DPRX have four lanes, two symbols per lane and four pixels per clock at 10 bits per component. The line rates are RBR, HBR, HBR2 and HBR3.

LEDs

LED	Description
GPIO_LED_0	System clock heartbeat (only when the PL is out of reset)
GPIO_LED_1	Video clock heartbeat
GPIO_LED_2	GT reference clock heartbeat
GPIO_LED_3	QPLL1 lock (transmitters)
GPIO_LED_4	TX reset done
GPIO_LED_5	RX reset done

Running on the ZCU102

Setup

• Mount the Tentiva on the FMC HPC0 connector of the ZCU102.
• Connect the JTAG (micro USB) of the ZCU102 to the host computer.
• Connect the UART (USB) of the Tentiva to the host computer.
• Connect a DisplayPort sink (monitor) to the DPTX connector and, for the pass-through, a DisplayPort source to the DPRX connector.

FMC voltage

At power-up the ZCU102 system controller reads the FMC EEPROM and sets the FMC voltage (VADJ). The EEPROM on the Tentiva FMC baseboard has a different layout and as a result the ZCU102 system controller doesn’t power the FMC voltage. For correct operation the FMC VADJ has to be set to 1.8V manually. Use the ZCU102 system controller GUI to set the FMC VADJ voltage.

Click here for more information on the ZCU102 system controller GUI.

Build

The gateware is built with Vivado 2025.1, the application with the Arm GNU toolchain (aarch64-none-elf). The build script of the application downloads the toolchain when it is not installed.

• Gateware: in amd/gateware/syn/zu9eg_zcu102 run vivado -mode batch -source ../../ref/zu9eg_zcu102/build_proj.tcl. This writes the bitstream and the hardware platform (.xsa) with the processing system initialization.
• Application: amd/software/build/dp_app/build.sh zu9eg_zcu102

Program

amd/scripts/prog_fpga.sh --board zu9eg_zcu102 configures the board over JTAG with xsdb (Vitis): it resets the system, configures the PL with the bitstream, initializes the processing system (psu_init from the hardware platform), loads the application into the on-chip memory and starts it on Cortex-A53 core 0. With --host <host> the script uses the hardware server of a remote computer. The application is not stored in flash; program the board again after a power cycle.

Console

Open the serial port of the Tentiva UART with a terminal program (115200 baud, 8N1). After start-up the application shows the version, initializes the Tentiva, the PHY, the VTB, the DPTX and the DPRX, and prints the menu. The DisplayPort events (link up / down, video up / down) are printed when they occur. When a sink is connected the DPTX trains the link, reads the EDID and starts the colorbar (1920 x 1080p60, or the format that was selected last).

Key	Command
q	DPTX ping
e	DPTX status
a	DPRX ping
d	DPRX status
f	DPRX HPD pulse
l	VTB status
s	PHY status
z	Colorbar. Select the video resolution (with the formats the sink supports), the color depth and the color space
x	Pass-through

Altera Agilex 5 modular development kit

The reference design runs on the Agilex 5 E-Series 065A modular development kit (A5ED065AB32AE1V). The DisplayPort TX and RX connectors are on the carrier board.

Hard processor system

The application runs bare metal on Cortex-A55 core 0 of the HPS, from the on-chip RAM (OCRAM). The application is the first stage boot loader: it is part of the bitstream and starts after the FPGA is configured. The DDR memory is not used. The application initializes the HPS clocks and the interconnect itself. The console is HPS UART0. The interrupts of the DPTX and DPRX go to the interrupt controller (GIC) of the HPS.

Programmable logic

The IP-cores and peripherals are connected to the lightweight HPS to FPGA bridge (Platform Designer). The system clock is 100 MHz.

Address	Peripheral	Description
0x2000_0010	PHY control	PIO. Transceiver resets
0x2000_0020	PHY status	PIO. Transceiver status
0x2000_0040	PIO out	PIO. DPTX and DPRX reset
0x2000_0050	PIO in	PIO. Design parameters
0x2000_1000	DPTX	DisplayPort transmitter
0x2000_2000	VTB	Video toolbox
0x2000_3000	Video PLL	Video clock PLL
0x2000_4000	DPRX	DisplayPort receiver
0x2000_5000	I2C	I2C controller (DisplayPort redrivers)
0x2040_0000	PHY reconfiguration	Reconfiguration interface of the transceiver

The PHY is the GTS transceiver bank 4A with the 150 MHz reference clock of the Si549 oscillator, see the PHY page. The video clock (pixel clock / 4) comes from a PLL in the FPGA, the application sets it for the video format. In the pass-through the PLL runs slightly faster and the clock recovery of the VTB drops the surplus clock cycles with a clock enable. The DPTX and DPRX have four lanes, two symbols per lane and four pixels per clock at 10 bits per component. The line rates are RBR, HBR, HBR2 and HBR3.

Build

The gateware is built with Quartus Prime Pro 26.1, the application with the Arm GNU toolchain (aarch64-none-elf).

• Gateware: in altera/gateware/syn/ag5e_065a_mdk run quartus_sh -t ../../ref/ag5e_065a_mdk/build_proj.tcl
• Application: altera/software/build/dp_app/build.sh. The script builds the application and adds it to the bitstream (dp_ref_alt_ag5e_065a_mdk_hps.sof).

Program

altera/scripts/prog_fpga.sh programs the bitstream with the application over JTAG (USB-Blaster III on the USB port of the board). The application starts after the configuration.

Console

The USB port of the board also has the HPS UART (115200 baud, 8N1). The menu is the same as on the ZCU102, with the extra command v to set the TX voltage swing and pre-emphasis.

Lattice Avant Versa board

The reference design runs on the Lattice Avant Versa board (LAV-AT-X70-1LFG1156C) with the Tentiva on the FMC connector.

Processor

The application runs on the RISC-V MC soft processor of Lattice Propel, with a system memory of 128 KB. The application is in the bitstream (the initial contents of the system memory). The UART, the I2C controller and a GPIO are Propel peripherals; the DPTX, DPRX, VTB and PHY controller are connected through the APB ports of the Propel interconnect. The system clock is 50 MHz. The Tentiva is on channel 7 of the I2C mux (address 0x70) of the Versa board.

Address	Peripheral	Description
0x4000_0000	GPIO	Propel GPIO
0x4000_1000	UART	Propel UART (console)
0x4000_2000	DPTX	DisplayPort transmitter
0x4000_3000	DPRX	DisplayPort receiver
0x4000_4000	VTB	Video toolbox
0x4000_5000	PHY	PHY controller (LMMI)
0x4000_6000	I2C	Propel I2C controller

The PHY is the MPPHY with the 135 MHz reference clock of the Tentiva, see the PHY page. The DPTX and DPRX have four lanes, four symbols per lane and four pixels per clock at 10 bits per component. The line rates are RBR, HBR, HBR2 and HBR3.

Build

The gateware is built with Lattice Radiant 2026.1, the application with Lattice Propel 2026.1.

• Gateware: in lsc/gateware/syn/lav_g70_versa_evn run radiantc ../../ref/lav_g70_versa_evn/build_proj.tcl, then synthesis, map, place & route and bitstream.
• Application: build the Propel project lsc/software/workspace/dp_app_lav.
• Put the application into the bitstream with lsc/script/eco_app.sh --board lav. This updates the system memory with the Radiant ECO, without a new place & route. Always run it after a full Radiant build: the build keeps the application image that Propel had when the SoC was generated.

Program

Program the bitstream (_eco.bit) over JTAG (mini USB of the Versa board) with the Radiant Programmer.

Console

The console is the UART of the Tentiva (115200 baud, 8N1). The commands are q / e (DPTX ping / status), a / d (DPRX ping / status), f (DPRX HPD: unplug, plug or pulse), l (VTB status), z (colorbar), x (pass-through) and c (select the EDID of the DPRX).

Lattice CertusPro-NX evaluation board