Reference Design

Introduction

The reference design shows the DisplayPort TX (DPTX) and DisplayPort RX (DPRX) IP-cores in a complete system. It consists of the DPTX, the DPRX, the Video Toolbox (VTB), the PHY and the application. The VTB is a collection of video helper modules. It has a timing generator, colorbar generator, FIFO and video clock recovery.

The application runs on the processor of the FPGA vendor: the Arm Cortex-A53 of the processing system on the AMD Zynq UltraScale+, the Arm Cortex-A55 of the hard processor system (HPS) on the Altera Agilex 5 and the RISC-V MC soft processor of Lattice Propel on the Lattice FPGAs. The application processor runs the application code and the DisplayPort IP-core host driver (see Driver). It controls the IP-cores and the other peripherals through a memory mapped bus. The link training, AUX and hot plug handling are done by the policy maker inside the DPTX and DPRX IP-cores, so the application only handles the events of the IP-cores.

The reference design has two operation modes; colorbar and pass-through. In colorbar mode the test pattern, generated by the VTB, is transmitted by the DPTX to the DisplayPort sink device. When the pass-through mode is selected, the video coming from the DisplayPort source is captured by the DPRX. Then the video is forwarded to the DPTX through the VTB. The clock recovery of the VTB steers the video clock, so the DPTX video runs at the frequency of the DisplayPort source.

The I2C controller configures the reference clock synthesizers on the Tentiva (PHY and video clocks), or on the Agilex 5 the DisplayPort redrivers of the board. The PHY controller accesses the transceiver registers (DRP on AMD, reconfiguration interface on Altera, LMMI on Lattice) and controls the transceiver resets and line rate.

Note

The AMD and Lattice reference designs use the Tentiva board. Tentiva is a video FMC board with DisplayPort sink and source connectors. Mount the Tentiva board on the FMC connector of the FPGA development board. Use the plastic screws to secure the Tentiva board. The Altera Agilex 5 modular development kit has DisplayPort connectors on the board and doesn't need the Tentiva.

The reference design is available for the following platforms;

Repository

The reference designs are in the reference folder of the DisplayPort repository, one folder per vendor (reference/amd, reference/altera and reference/lsc). Every vendor folder has the project scripts of the gateware, the application and a README with the build steps. The DisplayPort IP-cores are in gateware/src; the host driver and the policy maker images, which the application loads into the IP-cores at start-up, are in software. The output of the vendor tools (block design, Platform Designer system, Propel SoC and IP) is not in the repository: the project scripts create it.

Console

The application has a menu on the UART. Open the serial port with a terminal program (115200 baud, 8N1). After start-up the application shows the version, initializes the board, the PHY, the VTB, the DPTX and the DPRX, and prints the menu. The DisplayPort events (link up / down, video up / down) are printed when they occur. When a sink is connected the DPTX trains the link, reads the EDID and starts the colorbar in the preferred format of the sink that fits the link (or 1920 x 1080p60).

KeyCommandDesigns
qDPTX pingAll
eDPTX statusAll
aDPRX pingAll
dDPRX statusAll
fDPRX hot plug. AMD and Altera: HPD pulse. Lattice: unplug, plug or pulseAll
lVTB statusAll
zColorbar. Select the video resolution (the list shows the formats the sink and the link support), the color depth and the color spaceAll
xPass-throughAll
cSelect the video resolutions of the DPRX EDIDLattice

AMD Zynq UltraScale+

The AMD reference design runs on two Zynq UltraScale+ boards with the Tentiva: the ZCU102 evaluation kit (XCZU9EG-FFVB1156-2) and the Enclustra Mercury+ XU6 module (XCZU4CG-SFVC784-1) on the Mercury+ ST1 base board. Both boards have the same design; the block diagram is shown below.

AMD Zynq UltraScale+ reference design

Figure 1: AMD Zynq UltraScale+ reference design

Processing system

The application runs bare metal on Cortex-A53 core 0 of the processing system (PS), from the on-chip memory (OCM, 256 KB). The DDR memory is not used. The console is PS UART0, which is routed through the EMIO to the UART of the Tentiva. The PS supplies the system clock (100 MHz) and the DRP clock of the transceivers (40 MHz) to the programmable logic (PL). The interrupts of the DPTX and DPRX go to the interrupt controller (GIC) of the PS.

Programmable logic

The low power domain master port (M_AXI_HPM0_LPD) of the PS connects through an AXI SmartConnect to an AXI GPIO and an AXI to APB bridge. The APB bridge has a port of 4 KB for every IP-core and peripheral. The address map is shown below.

AddressPeripheralDescription
0x8000_0000PIOAXI GPIO. Output: DPTX and DPRX reset. Input: pixels per clock and bits per component of the design
0x8000_1000DPTXDisplayPort transmitter
0x8000_2000VTBVideo toolbox
0x8000_3000PHYPHY controller (DRP, resets, line rate, voltage swing and pre-emphasis)
0x8000_4000DPRXDisplayPort receiver
0x8000_5000I2CI2C controller. On the ZCU102 the Tentiva is on channel 0 of the I2C mux U135

The PHY is a GTH transceiver quad with the 270 MHz reference clock of the Tentiva, see the PHY page. The receivers use the channel PLL (CPLL), the transmitters the quad PLL (QPLL1). The DPTX and DPRX have four lanes and four pixels per clock at 10 bits per component. The line rates are RBR, HBR, HBR2 and HBR3.

BoardTransceiversSymbols per lane
ZCU102GTH quad X1Y2 (bank 229), FMC HPC02
Mercury+ XU6GTH quad X0Y1, FMC of the Mercury+ ST14
LEDs
ZCU102Mercury+ XU6Description
GPIO_LED_0LED0System clock heartbeat (only when the PL is out of reset)
GPIO_LED_1LED1Video clock heartbeat
GPIO_LED_2LED2GT reference clock heartbeat
GPIO_LED_3LED3QPLL1 lock (transmitters)
GPIO_LED_4-TX reset done
GPIO_LED_5-RX reset done
Build

The gateware is built with Vivado 2025.1, the application with the Arm GNU toolchain 13.2 (aarch64-none-elf), cmake and ninja. The build script of the application downloads the toolchain when it is not installed. <board> is zu9eg_zcu102 or zu4cg_xu6_st1.

Program

The processing system is initialized by the debugger, so the board is programmed with the Vitis xsdb console. Extract psu_init.tcl from the hardware platform (unzip dp_ref_amd_<board>.xsa psu_init.tcl) and run in xsdb: 

connect
targets -set -nocase -filter {name =~ "*PSU*"}
rst -system
targets -set -nocase -filter {name =~ "*PL*"}
fpga -file dp_ref_amd_<board>.bit
targets -set -nocase -filter {name =~ "*PSU*"}
source psu_init.tcl
psu_init
psu_ps_pl_isolation_removal
psu_ps_pl_reset_config
targets -set -nocase -filter {name =~ "*A53*#0"}
rst -processor -clear-registers
dow dp_app.elf
con

This resets the system, configures the PL with the bitstream, initializes the processing system, and loads and starts the application on Cortex-A53 core 0. The application is not stored in flash; program the board again after a power cycle.

Running on the ZCU102

AMD ZCU102 board setup

Figure 2: AMD ZCU102 board setup

Setup
FMC voltage

At power-up the ZCU102 system controller reads the FMC EEPROM and sets the FMC voltage (VADJ). The EEPROM on the Tentiva FMC baseboard has a different layout and as a result the ZCU102 system controller doesn’t power the FMC voltage. For correct operation the FMC VADJ has to be set to 1.8V manually. Use the ZCU102 system controller GUI to set the FMC VADJ voltage.

Click here for more information on the ZCU102 system controller GUI.

Running on the Mercury+ XU6

Enclustra Mercury+ XU6 on the Mercury+ ST1 board setup

Figure 3: Enclustra Mercury+ XU6 on the Mercury+ ST1 board setup

Setup

Altera Agilex 5 modular development kit

The reference design runs on the Agilex 5 E-Series 065A modular development kit (A5ED065AB32AE1V). The DisplayPort TX and RX connectors are on the carrier board. The block diagram is shown below.

Altera Agilex 5 reference design

Figure 4: Altera Agilex 5 reference design

Hard processor system

The application runs bare metal on Cortex-A55 core 0 of the HPS, from the on-chip RAM (OCRAM). The application is the first stage boot loader: it is part of the bitstream, and the secure device manager (SDM) loads it after the FPGA is configured. The DDR memory is not used. The application initializes the HPS clocks and the interconnect itself. The console is HPS UART0. The interrupts of the DPTX and DPRX go to the interrupt controller (GIC) of the HPS.

Programmable logic

The IP-cores and peripherals are connected to the lightweight HPS to FPGA bridge (Platform Designer). The system clock is 100 MHz.

AddressPeripheralDescription
0x2000_0010PHY controlPIO. Transceiver resets
0x2000_0020PHY statusPIO. Transceiver status
0x2000_0040PIO outPIO. DPTX and DPRX reset
0x2000_0050PIO inPIO. Design parameters
0x2000_1000DPTXDisplayPort transmitter
0x2000_2000VTBVideo toolbox
0x2000_3000Video PLLVideo clock PLL
0x2000_4000DPRXDisplayPort receiver
0x2000_5000I2CI2C controller (DisplayPort redrivers)
0x2040_0000PHY reconfigurationReconfiguration interface of the transceiver

The PHY is the GTS transceiver bank 4A with the 150 MHz reference clock of the Si549 oscillator, see the PHY page. The video clock (pixel clock / 4) comes from a PLL in the FPGA, the application sets it for the video format. In the pass-through the PLL runs slightly faster and the clock recovery of the VTB drops the surplus clock cycles with a clock enable. The DPTX and DPRX have four lanes, two symbols per lane and four pixels per clock at 10 bits per component. The line rates are RBR, HBR, HBR2 and HBR3. The LED of the modular board is the system clock heartbeat (only when the FPGA is out of reset).

Setup
Altera Agilex 5 modular development kit board setup

Figure 5: Altera Agilex 5 modular development kit board setup

Build

The gateware is built with Quartus Prime Pro 26.1.1, the application with the Arm GNU toolchain 13.2 (aarch64-none-elf), cmake and ninja.

Program

Program dp_ref_alt_ag5e_065a_mdk_hps.sof over JTAG with the Quartus Programmer. The FPGA is the second device in the JTAG chain, after the Arm DAP. From the command line: quartus_pgm -c <cable> -m jtag -o "p;dp_ref_alt_ag5e_065a_mdk_hps.sof@2", where jtagconfig lists the cables. The application starts after the configuration. When the HPS stops responding, power cycle the board.

Lattice Avant and CertusPro-NX

The Lattice reference design runs on two boards with the Tentiva on the FMC connector: the Avant Versa board (LAV-AT-X70-1LFG1156C) and the CertusPro-NX evaluation board (LFCPNX-100-9LFG672C). Both boards have the same design; the block diagram is shown below.

Lattice reference design

Figure 6: Lattice reference design

Processor

The application runs on the RISC-V MC soft processor of Lattice Propel, with a system memory of 128 KB. The UART, the I2C controller and a GPIO are Propel peripherals; the DPTX, DPRX, VTB and PHY controller are connected through the APB ports of the Propel interconnect. The system clock is 50 MHz. On the Avant Versa board the Tentiva is on channel 7 of the I2C mux (address 0x70).

AddressPeripheralDescription
0x4000_0000GPIOPropel GPIO
0x4000_1000UARTPropel UART (console)
0x4000_2000DPTXDisplayPort transmitter
0x4000_3000DPRXDisplayPort receiver
0x4000_4000VTBVideo toolbox
0x4000_5000PHYPHY controller (LMMI)
0x4000_6000I2CPropel I2C controller

The transceivers use the 135 MHz reference clock of the Tentiva, see the PHY page. The DPTX and DPRX have four lanes, four symbols per lane and four pixels per clock at 10 bits per component.

BoardTransceiversDPTX line ratesDPRX line rates
Avant VersaMPPHYRBR, HBR, HBR2, HBR3RBR, HBR, HBR2, HBR3
CertusPro-NX evaluation boardSerDes (MPCS)RBR, HBR, HBR2HBR, HBR2
LEDs
LEDDescriptionBoards
0System clock heartbeatAvant, CertusPro-NX
1DPTX heartbeatAvant, CertusPro-NX
2DPRX heartbeatAvant, CertusPro-NX
3SerDes TX clock heartbeatCertusPro-NX
4SerDes RX clock heartbeatCertusPro-NX
5Video clock heartbeatCertusPro-NX
Build

The gateware is built with Lattice Radiant 2026.1, the SoC and the application with Lattice Propel 2026.1. The steps are for the Avant, with the CertusPro-NX names in brackets.

  1. Propel SoC: in reference/lsc/gateware/propel run propelbldc < create_dp_soc_lav.tcl (create_dp_soc_lfcpnx.tcl). This creates the SoC dp_soc_lav (dp_soc_lfcpnx).
  2. Application: start Propel SDK with the workspace reference/lsc/software/workspace, import the project dp_app_lav (dp_app_lfcpnx), generate its BSP from the SoC (gateware/propel/dp_soc_lav/sge/sys_env.xml) and build it.
  3. Gateware: create the folder reference/lsc/gateware/syn/lav_g70_versa_evn (lfcpnx_evn) and run in it radiantc ../../ref/lav_g70_versa_evn/build_proj.tcl. The script creates the Radiant project, generates the Lattice IP and runs synthesis, map, place & route and the bitstream generation.
Program

Program the bitstream over JTAG with the Radiant Programmer. Then load the application in one of two ways:

Running on the Avant Versa board

Lattice Avant Versa board setup

Figure 7: Lattice Avant Versa board setup

Setup

Running on the CertusPro-NX evaluation board

Lattice CertusPro-NX evaluation board setup

Figure 8: Lattice CertusPro-NX evaluation board setup

Setup
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